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fedl610421-01 issue date: apr.12, 2011 ML610421/ml610422 8-bit microcontroller with a built-in lcd driver 1/36 general description this lsi is a high-performance 8-bit cmos microcontroller into which rich peripheral circuits, such as synchronous serial port, uart, i 2 c bus interface (master), melody driver, battery level det ect circuit, rc oscillation type a/d converter, 12-bit successive approximation type a/d converter, and lcd driver, are incorporated around 8-bit cpu nx-u8/100. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. this lsi operates in both high/low-speed mode and power-saving mode, it is most suitable for battery operated products. for industrial use, ML610421p/ml610422p with the extended operating ambient temperature ranging from -40c to 85c are available. features ? cpu ? 8-bit risc cpu (cpu name: nx-u8/100) ? instruction system: 16-bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? minimum instruction execution time 30.5 ? s (@32.768 khz system clock) 0.24 4? s (@4.096 mhz system clock) ? internal memory ? internal 32kbbyte mask rom (16k ? 16 bits) (including unusable 1kbyte test area) ? internal 1kbyte data ram (1024 ? 8 bits), 1kbyte display allocation ram (1024 x 8bit) ? internal 100byte ram for display ? interrupt controller ? 2 non-maskable interrupt sources (inte rnal source: 1, external source: 1) ? 20 maskable interrupt sources (internal sources: 16, external sources: 4) ? time base counter ? low-speed time base counter ? 1 channel frequency compensation (compensation range: approx. ? 488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) ? high-speed time base counter ? 1 channel ? watchdog timer ? non-maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) ? timers ? 8 bits ? 4 channels (timer0-3: 16-bit x 2 configuration available by using timer0-1 or timer2-3) ? clock frequency measurement mode (in one channel of 16-bit configuration using timer2-3)
fedl610421-01 lapis semiconductor ML610421/ml610422 2/36 ? 1 khz timer ? 10 hz/1 hz interrupt function ? capture ? time base capture ? 2 channels (4096 hz to 32 hz) ? pwm ? resolution 16 bits ? 1 channel ? synchronous serial port ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? txd/rxd ? 1 channel ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? master function only ? fast mode (400 kbps@4mh ), standard mode (100 kbps@1mh , 50kbps@500khz) ? melody driver ? scale: 29 types (melody sound frequency: 508 hz to 32.768 khz) ? tone length: 63 types ? tempo: 15 types ? buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) ? rc oscillation type a/d converter ? 24-bit counter ? time division ? 2 channels ? successive approximation type a/d converter ? 12-bit a/d converter ? input ? 2 channels ? general-purpose ports ? non-maskable interrupt input port ? 1 channel ? input-only port ? 6 channels (including secondary functions) ? output-only port ? 3 channels (including secondary functions) ? input/output port ML610421: 22 channels (including secondary functions) ml610422: 14 channels (including secondary functions)
fedl610421-01 lapis semiconductor ML610421/ml610422 3/36 ? lcd driver ? dot matrix can be supported. ML610421: 400 dots max. (50 seg ? 8 com), 1/1 to 1/8 duty ml610422: 800 dots max. (50 seg ? 16 com) , 1/1 to 1/16 duty ? 1/3 or 1/4 bias (built-in bias generation circuit) ? frame frequency selecable (approx. 64 hz, 73 hz, 85 hz, and 102 hz) ? bias voltage multiplying clock selectable (8 types) ? contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? programmable display allocation function (available only when 1/1~1/8 duty is selected) ? reset ? reset through the reset_n pin ? power-on reset generation when powered on ? reset when oscillation stop of the low-speed clock is detected (ML610421b/ml610422b does not have this function) ? reset by the watchdog timer (wdt) overflow ? power supply voltage detect function ? judgment voltages: one of 16 levels ? judgment accuracy: ? 2% (typ.) ? clock ? low-speed clock: (this lsi can not guarantee the operation withoug low-speed clock) crystal oscillation (32.768 khz) ? high-speed clock: built-in rc oscillation (500 khz) built-in pll oscillation (8.192 mhz ? 2.5%), crystal/ceramic oscillation (4.096 mhz), external clock ? selection of high-speed clock mode by software: built-in rc oscillation, built-in pll oscillation, crystal/ceramic oscillation, external clock ? power management ? halt mode: instruction execution by cpu is suspended (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals.
fedl610421-01 lapis semiconductor ML610421/ml610422 4/36 ? shipment ? chip ML610421-xxxwa ml610422-xxxwa ML610421p-xxxwa ml610422p-xxxwa ML610421b- xxxwa ml610422b- xxxwa ? 120-pin plastic tqfp ML610421-xxxtbz03a ml610422-xxxtbz03a ML610421p-xxxtbz03a ml610422p-xxxtbz03a ML610421b- xxxtbz03a ml610422b- xxxtbz03a xxx: rom code number p: wide range temperature version b: low-speed clock oscillation stop detection reset un-carrying version ? guaranteed operating range ? operating temperature: ? 20? c to 70 ? c (p version: ???? c to +85 ? c) ? operating voltage: v dd = 1.1v to 3.6v, av dd = 2.2v to 3.6v
fedl610421-01 lapis semiconductor ML610421/ml610422 5/36 block diagram ML610421 block diagram figure 1 show the block diagram of the ML610421. "*" indicates the secondary function of each port. figure 1 ML610421 block diagram program memory (mask rom) 32kbyte ssio sck0* sin0* sout0* uart rxd0* txd0* i 2 c sda* scl* int 1 ram 1024byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 4 capture 2 int 1 pwm gpio p00 to p03 p10 to p11 p20 to p22 int 5 nmi p30 to p35 p40 to p47 pa0 to pa7 data-bus pwm0* melody int 1 md0* test reset_n osc xt0 xt1 osc0* osc1* lsclk* outclk* bld power av dd av ss v ddl lcd driver com0 to com7 seg0 to seg49 lcd bias v l1 , v l2 , v l3 , v l4 c1 , c2 , c3 , c4 12bit-adc ain0 , ain1 v ref rc-adc 2 cs0* in0* rs0* rt0* crt0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss v ddx 1khztc int 1 int 1 int 1 display ram 100byte display allocation ram 1024byte
fedl610421-01 lapis semiconductor ML610421/ml610422 6/36 ml610422 block diagram figure 2 show the block diagram of the ml610422. "*" indicates the secondary function of each port. figure 2 ml610422 block diagram program memory (mask rom) 32kbyte ssio sck0* sin0* sout0* uart rxd0* txd0* i 2 c sda* scl* int 1 ram 1024byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 int 1 int 1 wdt int 4 8bit timer 4 capture 2 int 1 pwm gpio p00 to p03 p10 to p11 p20 to p22 int 5 nmi p30 to p35 p40 to p47 data-bus pwm0* melody int 1 md0* test reset_n osc xt0 xt1 osc0* osc1* lsclk* outclk* bld power av dd av ss v ddl lcd driver com0 to com15 seg0 to seg49 lcd bias v l1 , v l2 , v l3 , v l4 c1, c2, c3, c4 12bit-adc ain0 , ain1 v ref rc-adc 2 cs0* in0* rs0* rt0* crt0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 3 psw elr1 3 lr ecsr1 3 dsr/csr pc greg 0 15 v dd v ss v ddx 1khztc int 1 int 1 int 1 display ram 100byte display allocation ram 1024byte
fedl610421-01 lapis semiconductor ML610421/ml610422 7/36 pin configuration ML610421 tqfp120 pin layout note: the assignment of the pads p30 to p35 are not in order. figure 3 ML610421 tqfp120 pin configuration reset _ n 1pin 120pin 30pin 31pin 60pin 61pin 91pin 90pin pa6 pa7 p20 p21 p22 p40 p41 vss pa5 pa4 pa3 pa2 pa1 pa0 com7 com6 com5 com4 com3 com2 com1 com0 seg49 ( nc ) avss ( nc ) vref ain0 ain1 avdd seg6 seg5 seg4 seg3 seg2 seg1 seg0 vdd p11 (nc) p10 vss p03 p02 p01 p00 c4 c3 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg18 seg17 seg16 seg15 seg14 p42 p43 p44 p45 p46 p30 p31 p34 p32 p33 p35 test vdd vddl vss vddx xt0 vl1 vl3 vl2 nmi vss xt1 vl4 c1 c2 p47 nc ( nc ) seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg19 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 96 97 98 99 100 101 102 91 92 93 94 95 45 44 43 42 41 40 39 38 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 37 36 35 34 33 32 31 89 88 87 86 85 84 82 81 80 79 78 77 76 75 74 73 72 71 66 64 65 67 68 69 63 62 61 83 90 70 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 4 5 6 7 28 29 30
fedl610421-01 lapis semiconductor ML610421/ml610422 8/36 ml610422 tqfp120 pin layout no te: the assignment of the pads p30 to p35 are not in order. figure 4 ml610422 tqfp120 pin configuration reset_n 1pin 120pin 30pin 31pin 60pin 61pin 91pin 90pin com14 com15 p20 p21 p22 p40 p41 vss com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 seg49 (nc) avss ( nc ) vref ain0 ain1 avdd seg6 seg5 seg4 seg3 seg2 seg1 seg0 vdd p11 ( nc ) p10 vss p03 p02 p01 p00 c4 c3 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg18 seg17 seg16 seg15 seg14 p42 p43 p44 p45 p46 p30 p31 p34 p32 p33 p35 test vdd vddl vss vddx xt0 vl1 vl3 vl2 nmi vss xt1 vl4 c1 c2 p47 nc ( nc ) seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg19 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 96 97 98 99 100 101 102 91 92 93 94 95 45 44 43 42 41 40 39 38 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 37 36 35 34 33 32 31 89 88 87 86 85 84 82 81 80 79 78 77 76 75 74 73 72 71 66 64 65 67 68 69 63 62 61 83 90 70 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 4 5 6 7 28 29 30
fedl610421-01 lapis semiconductor ML610421/ml610422 9/36 ML610421 chip pin layout & dimension note: the assignment of the pads p30 to p35 are not in order. chip size: 2.80 mm ? 2.86 mm pad count: 115 pins minimum pad pitch: 80 ? m pad aperture: 70 ? m ? 70 ? m chip thickness: 350 ? m voltage of the rear side of chip: v ss level figure 5 ML610421 chip layout & dimension
fedl610421-01 lapis semiconductor ML610421/ml610422 10/36 ml610422 chip pin layout & dimension note: the assignment of the pads p30 to p35 are not in order. chip size: 2.80 mm ? 2.86 mm pad count: 115 pins minimum pad pitch: 80 ? m pad aperture: 70 ? m ? 70 ? m chip thickness: 350 ? m voltage of the rear side of chip: v ss level figure 6 ml610422 chip layout & dimension
fedl610421-01 lapis semiconductor ML610421/ml610422 11/36 ML610421 pad coordinates t able 1 ML610421 pad coordinates chip center: x=0,y=0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 reset_n -1090 -1324 51 seg12 1294 630 101 pa4 -1294 60 2 p42 -1010 -1324 52 seg13 1294 710 102 pa5 -1294 -20 3 p43 -930 -1324 53 seg14 1294 790 103 pa6 -1294 -100 4 p44 -850 -1324 54 seg15 1294 870 104 pa7 -1294 -180 5 p45 -770 -1324 55 seg16 1294 950 105 p20 -1294 -270 6 p46 -690 -1324 56 seg17 1294 1030 106 p21 -1294 -350 7 p47 -610 -1324 57 seg18 1294 1110 107 p22 -1294 -430 8 p30 -530 -1324 58 seg19 1160 1324 108 p40 -1294 -510 9 p31 -450 -1324 59 seg20 1080 1324 109 p41 -1294 -590 10 p34 -370 -1324 60 seg21 1000 1324 110 vss -1294 -670 11 p32 -290 -1324 61 seg22 920 1324 111 avss -1294 -750 12 p33 -210 -1324 62 seg23 840 1324 112 vref -1294 -830 13 p35 -130 -1324 63 seg24 760 1324 113 ain0 -1294 -910 14 test -50 -1324 64 seg25 680 1324 114 ain1 -1294 -1082 15 vdd 30 -1324 65 seg26 600 1324 115 avdd -1294 -1162 16 vddl 110 -1324 66 seg27 520 1324 17 vss 190 -1324 67 seg28 440 1324 18 vddx 270 -1324 68 seg29 360 1324 19 xt0 350 -1324 69 seg30 280 1324 20 xt1 510 -1324 70 seg31 200 1324 21 vss 590 -1324 71 seg32 120 1324 22 nmi 670 -1324 72 seg33 40 1324 23 vl1 750 -1324 73 seg34 -40 1324 24 vl2 830 -1324 74 seg35 -120 1324 25 vl3 910 -1324 75 seg36 -200 1324 26 vl4 990 -1324 76 seg37 -280 1324 27 c1 1070 -1324 77 seg38 -360 1324 28 c2 1150 -1324 78 seg39 -440 1324 29 c3 1294 -1220 79 seg40 -520 1324 30 c4 1294 -1140 80 seg41 -600 1324 31 p00 1294 -1050 81 seg42 -680 1324 32 p01 1294 -970 82 seg43 -760 1324 33 p02 1294 -890 83 seg44 -840 1324 34 p03 1294 -810 84 seg45 -920 1324 35 vss 1294 -730 85 seg46 -1000 1324 36 p10 1294 -650 86 seg47 -1080 1324 37 p11 1294 -490 87 seg48 -1160 1324 38 vdd 1294 -410 88 seg49 -1294 1110 39 seg0 1294 -330 89 com0 -1294 1030 40 seg1 1294 -250 90 com1 -1294 950 41 seg2 1294 -170 91 com2 -1294 870 42 seg3 1294 -90 92 com3 -1294 790 43 seg4 1294 -10 93 com4 -1294 710 44 seg5 1294 70 94 com5 -1294 630 45 seg6 1294 150 95 com6 -1294 550 46 seg7 1294 230 96 com7 -1294 470 47 seg8 1294 310 97 pa0 -1294 380 48 seg9 1294 390 98 pa1 -1294 300 49 seg10 1294 470 99 pa2 -1294 220 50 seg11 1294 550 100 pa3 -1294 140
fedl610421-01 lapis semiconductor ML610421/ml610422 12/36 ml610422 pad coordinates t able 2 ml610422 pad coordinates chip center: x=0,y=0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 reset_n -1090 -1324 51 seg12 1294 630 101 com12 -1294 60 2 p42 -1010 -1324 52 seg13 1294 710 102 com13 -1294 -20 3 p43 -930 -1324 53 seg14 1294 790 103 com14 -1294 -100 4 p44 -850 -1324 54 seg15 1294 870 104 com15 -1294 -180 5 p45 -770 -1324 55 seg16 1294 950 105 p20 -1294 -270 6 p46 -690 -1324 56 seg17 1294 1030 106 p21 -1294 -350 7 p47 -610 -1324 57 seg18 1294 1110 107 p22 -1294 -430 8 p30 -530 -1324 58 seg19 1160 1324 108 p40 -1294 -510 9 p31 -450 -1324 59 seg20 1080 1324 109 p41 -1294 -590 10 p34 -370 -1324 60 seg21 1000 1324 110 vss -1294 -670 11 p32 -290 -1324 61 seg22 920 1324 111 avss -1294 -750 12 p33 -210 -1324 62 seg23 840 1324 112 vref -1294 -830 13 p35 -130 -1324 63 seg24 760 1324 113 ain0 -1294 -910 14 test -50 -1324 64 seg25 680 1324 114 ain1 -1294 -1082 15 vdd 30 -1324 65 seg26 600 1324 115 avdd -1294 -1162 16 vddl 110 -1324 66 seg27 520 1324 17 vss 190 -1324 67 seg28 440 1324 18 vddx 270 -1324 68 seg29 360 1324 19 xt0 350 -1324 69 seg30 280 1324 20 xt1 510 -1324 70 seg31 200 1324 21 vss 590 -1324 71 seg32 120 1324 22 nmi 670 -1324 72 seg33 40 1324 23 vl1 750 -1324 73 seg34 -40 1324 24 vl2 830 -1324 74 seg35 -120 1324 25 vl3 910 -1324 75 seg36 -200 1324 26 vl4 990 -1324 76 seg37 -280 1324 27 c1 1070 -1324 77 seg38 -360 1324 28 c2 1150 -1324 78 seg39 -440 1324 29 c3 1294 -1220 79 seg40 -520 1324 30 c4 1294 -1140 80 seg41 -600 1324 31 p00 1294 -1050 81 seg42 -680 1324 32 p01 1294 -970 82 seg43 -760 1324 33 p02 1294 -890 83 seg44 -840 1324 34 p03 1294 -810 84 seg45 -920 1324 35 vss 1294 -730 85 seg46 -1000 1324 36 p10 1294 -650 86 seg47 -1080 1324 37 p11 1294 -490 87 seg48 -1160 1324 38 vdd 1294 -410 88 seg49 -1294 1110 39 seg0 1294 -330 89 com0 -1294 1030 40 seg1 1294 -250 90 com1 -1294 950 41 seg2 1294 -170 91 com2 -1294 870 42 seg3 1294 -90 92 com3 -1294 790 43 seg4 1294 -10 93 com4 -1294 710 44 seg5 1294 70 94 com5 -1294 630 45 seg6 1294 150 95 com6 -1294 550 46 seg7 1294 230 96 com7 -1294 470 47 seg8 1294 310 97 com8 -1294 380 48 seg9 1294 390 98 com9 -1294 300 49 seg10 1294 470 99 com10 -1294 220 50 seg11 1294 550 100 com11 -1294 140
fedl610421-01 lapis semiconductor ML610421/ml610422 13/36 pin list pad no. primary function secondary function tertiary function 422 421 pin name i/o function pin name i/o function pin name i/o function 17,21, 35,110 17,21, 3 5,110 vss ? negative power supply pin ? ? ? ? ? ? 15,38 15,38 v dd ? positive power supply pin ? ? ?? ? ? ?? 16 16 v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? ? ? 18 18 v ddx ? power supply pin for low-speed oscillation (internally generated) ? ? ? ? ? ? 111 111 av ss ? negative power supply pin for successive approximation type adc ? ? ? ? ? ? 115 115 av dd ? positive power supply pin for successive approximation type adc ? ? ? ? ? ? 23 23 v l1 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 24 24 v l2 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 25 25 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 26 26 v l4 ? power supply pin for lcd bias (internally generated) ? ? ? ? ? ? 27 27 c1 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 28 28 c2 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 29 29 c3 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 30 30 c4 ? capacitor connection pin for lcd bias generation ? ? ? ? ? ? 14 14 test i input pin for testing ? ? ? ? ? ? 1 1 reset_ n i reset input pin ? ? ? ? ? ? 19 19 xt0 i low-speed clock oscillation pin ? ? ? ? ? ? 20 20 xt1 o low-speed clock oscillation pin ? ? ? ? ? ? 112 112 v ref ? reference power supply pin for successive approximation type adc ? ? ? ? ? ?
fedl610421-01 lapis semiconductor ML610421/ml610422 14/36 pad no. primary function secondary function tertiary function 422 421 pin name i/o function pin name i/o function pin name i/o function 113 113 ain0 i successive approximation type adc input ? ? ? ? ? ? 114 114 ain1 i successive approximation type adc input ? ? ? ? ? ? 22 22 nmi i non-maskable interrupt pin ? ? ? ? ? ? 31 31 p00/exi 0/cap0 i input port, external interrupt 0, capture 0 input ? ? ? ? ? ? 32 32 p01/exi 1/cap1 i input port, external interrupt 1, capture 1 input ? ? ? ? ? ? 33 33 p02/exi 2/rxd0 i input port, external interrupt 2, uart0 receive ? ? ? ? ? ? 34 34 p03/exi 3 i input port, external interrupt 3 ? ? ? ? ? ? 36 36 p10 i input port osc0 i high-speed oscillation ? ? ? 37 37 p11 i input port osc1 o high-speed oscillation ? ? ? 105 105 p20/ led0 o output port lsclk o low-speed clock output ? ? ? 106 106 p21/ led1 o output port outclk o high-speed clock output ? ? ? 107 107 p22/ led2 o output port md0 o melody output ? ? ? 8 8 p30 i/o input/output port in0 i rc type adc0 oscillation input pin ? ? ? 9 9 p31 i/o input/output port cs0 o rc type adc0 reference capacitor connection pin ? ? ? 10 10 p34 i/o input/output port rct0 o rc type adc0 resistor/capacitor sensor connection pin pwm0 o pwm output 11 11 p32 i/o input/output port rs0 o rc type adc0 reference resistor connection pin ? ? ? 12 12 p33 i/o input/output port rt0 o rc type adc0 resistor sensor connection pin ? ? ? 13 13 p35 i/o input/output port rcm o rc type adc oscillation monitor ? ? ? 108 108 p40 i/o input/output port sda i/o i 2 c data input/output sin0 i ssio data input 109 109 p41 i/o input/output port scl i/o i 2 c clock input/output sck0 i/o ssio synchronous clock 2 2 p42 i/o input/output port rxd0 i uart data input sout0 i ssio data output 3 3 p43 i/o input/output port txd0 o uart data output pwm0 o pwm output 4 4 p44/t02 p0ck i/o input/output port, timer 0/timer 2/pwm0 external clock input in1 i rc type adc1 oscillation input pin sin0 i ssio0 data input 5 5 p45/t13 p1ck i/o input/output port, timer 1/timer 3 external clock input cs1 o rc type adc1 reference capacitor connection pin sck0 i/o ssio0 synchronous clock 6 6 p46 i/o input/output port rs1 o rc type adc1 reference resistor connection pin sout0 o ssio0 data output 7 7 p47 i/o input/output port rt1 o rc type adc1 resistor sensor connection pin ? ? ? ? 97 pa0 i/o input/output port ? ? ? ? ? ? ? 98 pa1 i/o input/output port ? ? ? ? ? ? ? 99 pa2 i/o input/output port ? ? ? ? ? ? ? 100 pa3 i/o input/output port ? ? ? ? ? ? ? 101 pa4 i/o input/output port ? ? ? ? ? ?
fedl610421-01 lapis semiconductor ML610421/ml610422 15/36 pad no. primary function secondary function tertiary function 422 421 pin name i/o function pin name i/o function pin name i/o function ? 102 pa5 i/o input/output port ? ? ? ? ? ? ? 103 pa6 i/o input/output port ? ? ? ? ? ? ? 104 pa7 i/o input/output port ? ? ? ? ? ? 89 89 com0 o lcd common pin ? ? ? ? ? ? 90 90 com1 o lcd common pin ? ? ? ? ? ? 91 91 com2 o lcd common pin ? ? ? ? ? ? 92 92 com3 o lcd common pin ? ? ? ? ? ? 93 93 com4 o lcd common pin ? ? ? ? ? ? 94 94 com5 o lcd common pin ? ? ? ? ? ? 95 95 com6 o lcd common pin ? ? ? ? ? ? 96 96 com7 o lcd common pin ? ? ? ? ? ? 97 ? com8 o lcd common pin ? ? ? ? ? ? 98 ? com9 o lcd common pin ? ? ? ? ? ? 99 ? com10 o lcd common pin ? ? ? ? ? ? 100 ? com11 o lcd common pin ? ? ? ? ? ? 101 ? com12 o lcd common pin ? ? ? ? ? ? 102 ? com13 o lcd common pin ? ? ? ? ? ? 103 ? com14 o lcd common pin ? ? ? ? ? ? 104 ? com15 o lcd common pin ? ? ? ? ? ? 39 39 seg0 o lcd segment pin ? ? ? ? ? ? 40 40 seg1 o lcd segment pin ? ? ? ? ? ? 41 41 seg2 o lcd segment pin ? ? ? ? ? ? 42 42 seg3 o lcd segment pin ? ? ? ? ? ? 43 43 seg4 o lcd segment pin ? ? ? ? ? ? 44 44 seg5 o lcd segment pin ? ? ? ? ? ? 45 45 seg6 o lcd segment pin ? ? ? ? ? ? 46 46 seg7 o lcd segment pin ? ? ? ? ? ? 47 47 seg8 o lcd segment pin ? ? ? ? ? ? 48 48 seg9 o lcd segment pin ? ? ? ? ? ? 49 49 seg10 o lcd segment pin ? ? ? ? ? ? 50 50 seg11 o lcd segment pin ? ? ? ? ? ? 51 51 seg12 o lcd segment pin ? ? ? ? ? ? 52 52 seg13 o lcd segment pin ? ? ? ? ? ? 53 53 seg14 o lcd segment pin ? ? ? ? ? ? 54 54 seg15 o lcd segment pin ? ? ? ? ? ? 55 55 seg16 o lcd segment pin ? ? ? ? ? ? 56 56 seg17 o lcd segment pin ? ? ? ? ? ? 57 57 seg18 o lcd segment pin ? ? ? ? ? ? 58 58 seg19 o lcd segment pin ? ? ? ? ? ? 59 59 seg20 o lcd segment pin ? ? ? ? ? ? 60 60 seg21 o lcd segment pin ? ? ? ? ? ? 61 61 seg22 o lcd segment pin ? ? ? ? ? ? 62 62 seg23 o lcd segment pin ? ? ? ? ? ? 63 63 seg24 o lcd segment pin ? ? ? ? ? ? 64 64 seg25 o lcd segment pin ? ? ? ? ? ? 65 65 seg26 o lcd segment pin ? ? ? ? ? ? 66 66 seg27 o lcd segment pin ? ? ? ? ? ? 67 67 seg28 o lcd segment pin ? ? ? ? ? ? 68 68 seg29 o lcd segment pin ? ? ? ? ? ? 69 69 seg30 o lcd segment pin ? ? ? ? ? ? 70 70 seg31 o lcd segment pin ? ? ? ? ? ? 71 71 seg32 o lcd segment pin ? ? ? ? ? ? 72 72 seg33 o lcd segment pin ? ? ? ? ? ?
fedl610421-01 lapis semiconductor ML610421/ml610422 16/36 pad no. primary function secondary function tertiary function 422 421 pin name i/o function pin name i/o function pin name i/o function 73 73 seg34 o lcd segment pin ? ? ? ? ? ? 74 74 seg35 o lcd segment pin ? ? ? ? ? ? 75 75 seg36 o lcd segment pin ? ? ? ? ? ? 76 76 seg37 o lcd segment pin ? ? ? ? ? ? 77 77 seg38 o lcd segment pin ? ? ? ? ? ? 78 78 seg39 o lcd segment pin ? ? ? ? ? ? 79 79 seg40 o lcd segment pin ? ? ? ? ? ? 80 80 seg41 o lcd segment pin ? ? ? ? ? ? 81 81 seg42 o lcd segment pin ? ? ? ? ? ? 82 82 seg43 o lcd segment pin ? ? ? ? ? ? 83 83 seg44 o lcd segment pin ? ? ? ? ? ? 84 84 seg45 o lcd segment pin ? ? ? ? ? ? 85 85 seg46 o lcd segment pin ? ? ? ? ? ? 86 86 seg47 o lcd segment pin ? ? ? ? ? ? 87 87 seg48 o lcd segment pin ? ? ? ? ? ? 88 88 seg49 o lcd segment pin ? ? ? ? ? ?
fedl610421-01 lapis semiconductor ML610421/ml610422 17/36 pin description pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors cdl and cgl are connected across this pin and v ss as required. ? ? osc0 i secondary ? osc1 o crystal/ceramic connection pin for high-speed clock. a crystal or ceramic is connected to this pin (4.1 mhz max.). capacitors cdh and cgh (see measuring circuit 1) are connected across this pin and v ss . this pin is used as the secondary function of the p10 pin(osc0) and p11 pin(osc1). secondary ? lsclk o low-speed clock output pin. this pin is used as the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00-p03 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p10-p11 i general-purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose output port p20-p22 o general-purpose output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general-purpose input/output port p30-p35 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p40-p47 i/o general-purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive pa0-pa7 i/o general-purpose input/output port. these pins are for the ML610421, but are not provided in the ml610422. primary positive
fedl610421-01 lapis semiconductor ML610421/ml610422 18/36 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/se condary positive i 2 c bus interface sda i/o i 2 c data input/output pin. this pin is used as the secondary function of the p40 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl i/o i 2 c clock output pin. this pin is used as the secondary function of the p41 pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/output pin. this pin is used as the tertiary function of the p41 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p40 or p44 pin. tertiary positive sout0 o synchronous serial data output pin. this pin is used as the tertiary function of the p42 or p46 pin. tertiary positive pwm pwm0 o pwm0 output pin. this pin is used as the tertiary function of the p43 or p34 pin. tertiary positive t02p0ck o pwm0 external clock input pin. this pin is used as the primary function of the p44 pin. primary ? external interrupt nmi i external non-maskable interrupt input pin. an interrupt is generated on both edges. primary positive/ negative exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00-p03 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t02p0ck i external clock input pin used for both timer 0 and timer 2. the clocks for these timers are selected by software. this pin is used as the primary function of the p44 pin. primary ? t13p1ck i external clock input pin used for both timer 1 and timer 3. the clocks for these timers are selected by software. this pin is used as the primary function of the p45 pin. primary ? melody md0 o melody/buzzer signal output pin. this pin is used as the secondary function of the p22 pin. secondary positive/ negative led drive led0-2 o nch open drain output pins to drive led. primary positive/ negative
fedl610421-01 lapis semiconductor ML610421/ml610422 19/36 pin name i/o description primary/ secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor connection pin. this pin is used as the secondary function of the p31 pin. secondary ? rs0 o this pin is used as the secondary function of the p32 pin which is the reference resistor connection pin of channel 0. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p33 pin. secondary ? rct0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p34 pin. secondary ? rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? successive approximation type a/d converter av ss ? negative power supply pin for successive approximation type a/d converter. ? ? av dd ? positive power supply pin for successive approximation type a/d converter. ? ? v ref ? reference power supply pin for successive approximation type a/d converter. ? ? ain0 i channel 0 analog input for successive approximation type a/d converter. ? ? ain1 i channel 1 analog input for successive approximation type a/d converter. ? ? lcd drive signal com0-7 o common output pins. ? ? com8-15 o common output pins. these pins are for the ml610422, but are not provided in the ML610421. ? ? seg0-49 o segment output pin. ? ? lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? ? ? v l4 ? power supply pins for lcd bias (internally generated). capacitors ca, cb, cc, and cd (see measuring circuit 1) are connected between v ss and v l1 , v l2 , v l3 , and v l4 , respectively. ? ? c1 ? ? ? c2 ? ? ? c3 ? ? ? c4 ? power supply pins for lcd bias (internally generated). capacitors c12 and c34 (see measuring circuit 1) are connected between c1 and c2 and between c3 and c4, respectively. ? ? for testing test i input pin for testing. a pull-down resistor is internally connected. ? ? power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors cl0 and cl1 (see measuring circuit 1) are connected between this pin and v ss . ? ? v ddx ? plus-side power supply pin (internally generated) for low-speed oscillation. capacitor cx (see measuring circuit 1) is connected between this pin and v ss . ? ?
fedl610421-01 lapis semiconductor ML610421/ml610422 20/36 termination of unused pins table 3 shows methods of terminating the unused pins. table 3 termination of unused pins pin recommended pin termination av dd v ss av ss v ss v ref v ss ain0, ain1 open v l1 , v l2 , v l3 , v l4 open c1, c2, c3, c4 open reset_n open test open nmi open p00 to p03 v dd or v ss p10 to p11 v dd p20 to p22 open p30 to p35 open p40 to p47 open pa0 to pa7 open com0 to 15 open seg0 to 49 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610421-01 lapis semiconductor ML610421/ml610422 21/36 electrical characteristics absolute maximum ratings (v ss = av ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 ?c ? 0.3 to +4.6 v power supply voltage 2 av dd ta = 25 ?c ? 0.3 to +4.6 v power supply voltage 3 v ddl ta = 25 ?c ? 0.3 to +3.6 v power supply voltage 4 v ddx ta = 25 ?c ? 0.3 to +3.6 v power supply voltage 5 v l1 ta = 25 ?c ? 0.3 to +1.75 v power supply voltage 6 v l2 ta = 25 ?c ? 0.3 to +3.5 v power supply voltage 7 v l3 ta = 25 ?c ? 0.3 to +5.25 v power supply voltage 8 v l4 ta = 25 ?c ? 0.3 to +7.0 v input voltage v in ta = 25 ?c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 ?c ? 0.3 to v dd +0.3 v output current 1 i out1 port3?a, ta = 25 ?c ? 12 to +11 ma output current 2 i out2 port2, ta = 25 ?c ? 12 to +20 ma power dissipation pd ta = 25 ? c 1.25 w storage temperature t stg ?? ? 55 to +150 ?c recommended operating conditions (v ss = av ss = 0v) parameter symbol condition range unit ML610421, ml610422 ?? 20 to +70 operating temperature t op ML610421p, ml610422p ?? 40 to +85 ? ?c v dd ?? 1.1 to 3.6 operating voltage av dd ?? 2.2 to 3.6 v v dd = 1.1 to 3.6v 30k to 36k v dd = 1.3 to 3.6v 30k to 650k operating frequency (cpu) f op v dd = 1.8 to 3.6v 30k to 4.2m hz low-speed crystal oscillation frequency f xtl ?? 32.768k hz c dl ?? 0 to 12 low-speed crystal oscillation external capacitor c gl ?? 0 to 12 pf high-speed crystal/ceramic oscillation frequency f xth ?? 4.0m / 4.096m hz c dh ?? 24 high-speed crystal oscillation external capacitor c gh ?? 24 pf c l0 ?? 1.0 ? 30% capacitor externally connected to v ddl pin c l1 ?? 0.1 ? 30% ? f capacitor externally connected to v ddx pin c x ?? 0.1 ? 30% ? f capacitors externally connected to v l1, 2, 3, 4 pins c a, b, c, d ?? 1.0 ? 30% ? f capacitors externally connected across c1 and c2 pins and across c3 and c4 pins c 12, c 34 ?? 1.0 ? 30% ? f
fedl610421-01 lapis semiconductor ML610421/ml610422 22/36 dc characteristics (1/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (1/5) rating parameter symbol condition min. typ. max. unit measuring circuit ta = 25 ?c typ. ? 10% 500 typ. ? 10% khz ta = ? 20 to +70 ?c typ. ? 25% 500 typ. ? 25% khz 500khz rc oscillation frequency f rc v dd = 1.3 to 3.6v ta = ? 40 to +85 ?c typ. ? 45% 500 typ. ? 45% khz pll oscillation frequency* 4 f pll lsclk = 32.768khz v dd = 1.8 to 3.6v -2.5% 8.192 +2.5% mhz low-speed crystal oscillation start time* 2 t xtl ?? ?? 0.3 2 s 500khz rc oscillation start time t rc ?? ?? 50 500 ? s high-speed crystal oscillation start time* 3 t xth v dd = 1.8 to 3.6v D 2 20 pll oscillation start time t pll v dd = 1.8 to 3.6v D 1 10 low-speed oscillation stop detect time *1 t stop ?? 0.2 3 20 ms reset pulse width p rst ?? 200 ?? ?? reset noise elimination pulse width p nrst ?? ?? ?? 0.3 ? s power-on reset activation power rise time t por ?? ?? ?? 10 ms 1 * 1 : when low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. * 2 : use 32.768khz crystal oscillator c-001r (epson toyocom) with capacitance c gl /c dl 0pf. * 3 : use 4.096mhz crystal oscillator hc49sfwb (kyocera). * 4 : 1024 clock average. reset reset_n reset_n pin reset vdd 0.9xv dd 0.1xv dd t por power on reset p rst vil1 vil1
fedl610421-01 lapis semiconductor ML610421/ml610422 23/36 dc characteristics (2/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (2/5) rating parameter symbol condition min. typ. max. unit measuring circuit cn4?0 = 00h 0.89 0.94 0.99 cn4?0 = 01h 0.91 0.96 1.01 cn4?0 = 02h 0.93 0.98 1.03 cn4?0 = 03h 0.95 1.00 1.05 cn4?0 = 04h 0.97 1.02 1.07 cn4?0 = 05h 0.99 1.04 1.09 cn4?0 = 06h 1.01 1.06 1.11 cn4?0 = 07h 1.03 1.08 1.13 cn4?0 = 08h 1.05 1.10 1.15 cn4?0 = 09h 1.07 1.12 1.17 cn4?0 = 0ah 1.09 1.14 1.19 cn4?0 = 0bh 1.11 1.16 1.21 cn4?0 = 0ch 1.13 1.18 1.23 cn4?0 = 0dh 1.15 1.20 1.25 cn4?0 = 0eh 1.17 1.22 1.27 cn4?0 = 0fh 1.19 1.24 1.29 cn4?0 = 10h 1.21 1.26 1.31 cn4?0 = 11h 1.23 1.28 1.33 cn4?0 = 12h 1.25 1.30 1.35 cn4?0 = 13h 1.27 1.32 1.37 cn4?0 = 14h *1 1.29 1.34 1.39 cn4?0 = 15h *1 1.31 1.36 1.41 cn4?0 = 16h *1 1.33 1.38 1.43 cn4?0 = 17h *1 1.35 1.40 1.45 cn4?0 = 18h *1 1.37 1.42 1.47 cn4?0 = 19h *1 1.39 1.44 1.49 cn4?0 = 1ah *1 1.41 1.46 1.51 cn4?0 = 1bh *1 1.43 1.48 1.53 cn4?0 = 1ch *1 1.45 1.50 1.55 cn4?0 = 1dh *1 1.47 1.52 1.57 cn4?0 = 1eh *1 1.49 1.54 1.59 v l1 voltage v l1 v dd = 3.0v, tj = 25 ?c cn4?0 = 1fh *1 1.51 1.56 1.61 v v l1 temperature deviation ? v l1 v dd = 3.0v ? ????? ? mv/ ?c v l1 voltage dependency ? v l1 v dd = 1.3 to 3.6v ?? 5 20 mv/v v l2 voltage * v l2 v dd = 3.0v, tj = 25 ?c 500k ? load (v l4 ? v ss ) typ. ? 10% v l1 ? 2 typ. +4% 1/3 bias v l1 ? 2 v l3 voltage * v l3 1/4 bias typ. ? 10% v l1 ? 3 typ. +4% 1/3 bias v l1 ? 3 v l4 voltage * v l4 v dd = 3.0v, tj = 25 ?c 500k ? load (v l4 ? v ss ) 1/4 bias typ. ? 10% v l1 ? 4 typ. +5% v lcd bias voltage generation time t bias ?? ?? ?? 600 ms 1 *1: when using 1/4 bias, the v l1 voltage is set to typ. 1.32 v (same voltage as in cn4?0 = 13h). *2: boost clock is 2khz(initial) for the bias generation. c12=c34=1uf.
fedl610421-01 lapis semiconductor ML610421/ml610422 24/36 dc characteristics (3/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (3/5) rating parameter symbol condition min. typ. max. unit measuring circuit ld2?0 = 0h 1.35 ld2?0 = 1h 1.4 ld2?0 = 2h 1.45 ld2?0 = 3h 1.5 ld2?0 = 4h 1.6 ld2?0 = 5h 1.7 ld2?0 = 6h 1.8 ld2?0 = 7h 1.9 ld2?0 = 8h 2.0 ld2?0 = 9h 2.1 ld2?0 = 0ah 2.2 ld2?0 = 0bh 2.3 ld2?0 = 0ch 2.4 ld2?0 = 0dh 2.5 ld2?0 = 0eh 2.7 bld threshold voltage v bld v dd = 1.35 to 3.6v ld2?0 = 0fh typ. ? 2% 2.9 typ. +2% v bld threshold voltage temperature deviation ? v bld v dd = 1.35 to 3.6v ?? ?? ? %/ ?c ta = 25? c ?? 0.15 0.50 ta = -20 to +70 ? c ?? ? 2.50 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. ta = -40 to +85 ? c ?? ?? 5.00 ? a ta = 25? c ?? 0.5 1.3 ta = -20 to +70 ? c ?? ? 3.5 supply current 2 idd2 cpu: in halt state (ltbc, wdt: operating * 3 * 5 ). high-speed oscillation: stopped. lcd/bias circuits: stopped. ta = -40 to +85 ? c ?? ?? 6.0 ? a ta = 25? c ?? 5 7 ta = -20 to +70 ? c ?? ? 12 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed oscillation: stopped. lcd/bias circuits: operating.* 2 ta = -40 to +85 ? c ?? ?? 16 ? a ta = 25? c ?? 70 85 ta = -20 to +70 ? c ?? ? 100 supply current 4 idd4 cpu: in 500khz cr operating state. lcd/bias circuits: operating.* 2 ta = -40 to +85 ? c ?? ?? 120 ? a ta = 25? c ?? 0.8 1.0 ta = -20 to +70 ? c ?? ? 1.2 supply current 5 idd5 cpu: in 4.096mhz operating state.* 2 * 3 pll: in oscillating state. lcd/bias circuits: operating. * 2 v dd = 1.8 to 3.6v ta = -40 to +85 ? c ?? ?? 1.2 ma supply current 6 idd6 cpu: in 4.096mhz operating state.* 2 ta = 25? c ?? 1.5 1.6 ma 1
fedl610421-01 lapis semiconductor ML610421/ml610422 25/36 ta = -20 to +70 ? c ?? ? 2.5 pll: in oscillating state. * 3 * 4 a/d: in operating state. lcd/bias circuits: operating. * 2 v dd = av dd = 3.0v ta = -40 to +85 ? c ?? ?? 2.5 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock: 1/128 lsclk (256hz) * 3 : use 32.768khz crystal oscillator c-001r (epson toyocom) with capacitance c gl /c dl 0pf. * 4 : use 4.096mhz crystal oscillator hc49sfwb (kyocera). * 5 : significant bits of blkcon0~blkcon4 registers are all ?1?. dc characteristics (4/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (4/5) rating parameter symbol condition min. typ. max. unit measuring circuit ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ?? ?? ioh1 = -0.1ma, v dd = 1.3 to 3.6v v dd ? 0.3 ?? ?? voh1 ioh1 = -0.03ma, v dd = 1.1 to 3.6v v dd ? 0.3 ?? ?? iol1 = +0.5ma, v dd = 1.8 to 3.6v ?? ?? 0.5 iol1 = +0.1ma, v dd = 1.3 to 3.6v ?? ?? 0.5 output voltage 1 (p20?p22/2 nd function is selected) (p30?p35) (p40?p47) (pa0?pa7) *1 vol1 iol1 = +0.03ma, v dd = 1.1 to 3.6v ?? ?? 0.3 ioh1 = ? 0.5ma, v dd = 1.8 to 3.6v v dd ? 0.5 ? ?? ? ioh1 = -0.1ma, v dd = 1.3 to 3.6v v dd ? 0.3 ? ?? ? voh2 ioh1 = -0.03ma, v dd = 1.1 to 3.6v v dd ? 0.3 ? ?? ? output voltage 2 (p20?p22/2 nd function is not selected) vol2 iol2 = +5ma, v dd = 1.8 to 3.6v ?? ?? 0.5 output voltage 3 (p40?p41) vol3 iol3 = +3ma, v dd = 2.0 to 3.6v (when i 2 c mode is selected) ?? ?? 0.4 voh4 ioh4 = ? 0.2ma, vl1=1.2v v l4 ? 0.2 ?? ?? vomh4 iomh4 = +0.2ma, vl1=1.2v ?? ?? v l3 +0.2 vomh4s iomh4s = ? 0.2ma, vl1=1.2v v l3 ? 0.2 ?? ?? vom4 iom4 = +0.2ma, vl1=1.2v ?? ?? v l2 +0.2 vom4s iom4s = ? 0.2ma, vl1=1.2v v l2 ? 0.2 ?? ?? voml4 ioml4 = +0.2ma, vl1=1.2v ?? ?? v l1 +0.2 voml4s ioml4s = ? 0.2ma, vl1=1.2v v l1 ? 0.2 ?? ?? output voltage 4 (com0?7) (com8?15) *2 (seg0?49) vol4 iol4 = +0.2ma, vl1=1.2v ?? ?? 0.2 v 2 iooh voh = v dd (in high-impedance state) ?? ?? 1 output leakage (p20?p22) (p30?p35) (p40?p47) (pa0?pa7) *1 iool vol = v ss (in high-impedance state) ? 1 ?? ?? ? a 3
fedl610421-01 lapis semiconductor ML610421/ml610422 26/36 iih1 vih1 = v dd 0 ?? 1 v dd = 1.8 to 3.6v ? 600 ? 300 ? 20 v dd = 1.3 to 3.6v ? 600 ? 300 -10 input current 1 (reset_n) iil1 vil1 = v ss v dd = 1.1 to 3.6v ? 600 ? ? 300 ? -2 v dd = 1.8 to 3.6v 20 ? 300 ? 600 v dd = 1.3 to 3.6v 10 ? 300 ? 600 iih1 vih1 = v dd v dd = 1.1 to 3.6v 2 ? 300 ? 600 input current 1 (test) iil1 vil1 = v ss -1 ???? v dd = 1.8 to 3.6v 2 30 200 v dd = 1.3 to 3.6v 0.2 30 200 iih2 vih2 = v dd (when pulled-down) v dd = 1.1 to 3.6v 0.01 30 200 v dd = 1.8 to 3.6v ? 200 ? 30 ? 2 v dd = 1.3 to 3.6v ? 200 ? 30 -0.2 iil2 vil2 = v ss (when pulled-up) v dd = 1.1 to 3.6v ? 200 ? ? 30? -0.01 iih2z vih2 = v dd (in high-impedance state) ?? ?? 1 input current 2 (nmi) (p00?p03) (p10?p11) (p30?p35) (p40?p47) (pa0?pa7) *1 iil2z vil2 = v ss (in high-impedance state) ? 1 ?? ?? ? a 4 *1: ML610421 only *2: ml610422 only dc characteristics (5/5) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) (5/5) rating parameter symbol condition min. typ. max. unit measuring circuit v dd = 1.3 to 3.6v ?? 0.7 ? v dd ?? v dd vih1 v dd = 1.1 to 3.6v ? 0.7 ? v dd ?? v dd v dd = 1.3 to 3.6v ?? 0 ?? 0.3 ? v dd input voltage 1 (reset_n) (test) (nmi) (p00?p03) (p10?p11) (p31?p35) (p40?p43) (p45?p47) (pa0?pa7) *1 vil1 v dd = 1.1 to 3.6v ? 0 ?? 0.2 ? v dd vih2 ? 0.7 ? v dd ? v dd input voltage 2 (p30, p44) vil2 ?? 0 ?? 0.3 ? v dd v 5 input pin capacitance (nmi) (p00?p03) (p10?p11) (p30?p35) (p40?p47) (pa0?pa7) *1 cin f = 10khz v rms = 50mv ta = 25 ?c ?? ?? 5 pf ?? *1: ML610421 only
fedl610421-01 lapis semiconductor ML610421/ml610422 27/36 measuring circuits measuring circuit 1 measuring circuit 2 xt0 xt1 p10/osc0 p11/osc1 32.768khz crystal 4.096mhz crystal c gh c dh a v dd av dd v ref v ddl v ddx c l1 c l0 c x v l1 c a v l2 c b v l3 c c v l4 c d v ss av ss c4 c3 c2 c1 c 12 c 34 c v : 1 ? f c l0 : 1 ? f c l1 : 0.1 ? f c x : 0.1 ? f c a ,c b ,c c ,c d : 1 ? f c 12 ,c 34 : 1 ? f c gh : 24pf c dh : 24pf 32.768khz crystal: c-001r (epson toyocom) 4.096mhz crystal: hc49sfwb (kyocera) c v input pins v v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v l4 v ss av ss vih vil output pins (*1) input logic circuit to determine the specified measuring conditions. (*2) measured at the specified output pins. (*2) (*1)
fedl610421-01 lapis semiconductor ML610421/ml610422 28/36 measuring circuit 3 measuring circuit 4 measuring circuit 5 input pins a v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v l4 v ss av ss output pins *3: measured at the specified output pins. (*3) input pins v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v l4 v ss av ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. (*1) waveform monitoring input pins a v dd av dd v ref v ddl v ddx v l1 v l2 v l3 v l4 v ss av ss vih vil output pins *1: input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) (*1)
fedl610421-01 lapis semiconductor ML610421/ml610422 29/36 ac characteristics (external interrupt) (v dd = 1.1 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 ?? 106.8 ? s ac characteristics (uart) (v dd = 1.3 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt ?? ?? brt* 1 ?? s receive baud rate t rbrt ?? brt* 1 ? 3% brt* 1 brt* 1 +3% s *1: baud rate period (including the error of the clock frequency selected) set with the uart0 baud rate register (ua0brtl,h) and the uart0 mode register 0 (ua0mod0). t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) nmi, p00?p03 (both-edge interrupt) t nul t nul t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt
fedl610421-01 lapis semiconductor ML610421/ml610422 30/36 ac characteristics (synchronous serial port) (v dd = 1.3 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit when rc oscillation is active* 2 (v dd = 1.3 to 3.6v) 10 ?? ?? ? s sclk input cycle (slave mode) t scyc when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) 1 ?? ?? ? s sclk output cycle (master mode) t scyc ?? ?? sclk* 1 ?? s when rc oscillation is active* 2 (v dd = 1.3 to 3.6v) 4 ?? ?? ? s sclk input pulse width (slave mode) t sw when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) 0.4 ?? ?? ? s sclk output pulse width (master mode) t sw ?? sclk* 1 ? 0.4 sclk* 1 ? 0.5 sclk* 1 ? 0.6 s when rc oscillation is active* 2 (v dd = 1.3 to 3.6v) ? ?? ?? 500 sout output delay time (slave mode) t sd when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) ? ?? ?? 240 ns when rc oscillation is active* 2 (v dd = 1.3 to 3.6v) ? ?? ?? 500 sout output delay time (master mode) t sd when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) ? ?? ?? 240 ns sin input setup time (slave mode) t ss ?? 80 ?? ?? ns when rc oscillation is active* 2 (v dd = 1.3 to 3.6v) ? 500 ?? ?? sin input setup time (master mode) t ss when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) ? 240 ?? ?? ns when rc oscillation is active* 2 (v dd = 1.3 to 3.6v) ? 300 ?? ?? sin input hold time t sh when high-speed oscillation is active* 3 (v dd = 1.8 to 3.6v) ? 80 ?? ?? ns * 1 : clock period selected with s0ck3?0 of the serial port 0 mode register (sio0mod1) * 2 : when rc oscillation is selected with oscm1?0 of the frequency control register (fcon0) * 3 : when crystal/ceramic oscillation, built-in pll oscillation, or external clock input is selected with oscm1?0 of the frequency control register (fcon0) t sd sclk0* sin0* sout0* *: indicates the secondar y function of the p ort. t sd t ss t sh t sw t sw t scyc
fedl610421-01 lapis semiconductor ML610421/ml610422 31/36 ac characteristics (i 2 c bus interface: standard mode 100khz) (v dd = 1.8 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ?? 0 ?? 100 khz scl hold time (start/restart condition) t hd:sta ?? 4.0 ?? ?? ? s scl ?l? level time t low ?? 4.7 ?? ?? ? s scl ?h? level time t high ?? 4.0 ?? ?? ? s scl setup time (restart condition) t su:sta ?? 4.7 ?? ?? ? s sda hold time t hd:dat ?? 0 ?? ? ? s sda setup time t su:dat ?? 0.25 ?? ?? ? s sda setup time (stop condition) t su:sto ?? 4.0 ?? ?? ? s bus-free time t buf ?? 4.7 ?? ?? ? s ac characteristics (i2c bus interface: fast mode 400khz) (v dd = 1.8 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ?? 0 ?? 400 khz scl hold time (start/restart condition) t hd:sta ?? 0.6 ?? ?? ? s scl ?l? level time t low ?? 1.3 ?? ?? ? s scl ?h? level time t high ?? 0.6 ?? ?? ? s scl setup time (restart condition) t su:sta ?? 0.6 ?? ?? ? s sda hold time t hd:dat ?? 0 ?? ? ? s sda setup time t su:dat ?? 0.1 ?? ?? ? s sda setup time (stop condition) t su:sto ?? 0.6 ?? ?? ? s bus-free time t buf ?? 1.3 ?? ?? ? s p41/scl p40/sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl610421-01 lapis semiconductor ML610421/ml610422 32/36 ac characteristics (rc oscillation a/d converter) (v dd = 1.3 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resistors for oscillation rs0, rs1, rt0, rt0-1,rt1 cs0, ct0, cs1 ? 740pf 1 ?? ?? k ? f osc1 resistor for oscillation = 1k ? 209.4 330.6 435.1 khz f osc2 resistor for oscillation = 10k ? 41.29 55.27 64.16 khz oscillation frequency vdd = 1.5v f osc3 resistor for oscillation = 100k ? 4.71 5.97 7.06 khz kf1 rt0, rt0-1, rt1 = 1khz 5.567 5.982 6.225 ? ? kf2 rt0, rt0-1, rt1 = 10khz 0.99 1 1.01 ? ? rs to rt oscillation frequency ratio *1 vdd = 1.5v kf3 rt0, rt0-1, rt1 = 100khz 0.104 0.108 0.118 ? ? f osc1 resistor for oscillation = 1k ? 407.3 486.7 594.6 khz ? f osc2 resistor for oscillation = 10k ? 49.76 59.28 72.76 khz ? oscillation frequency vdd = 3.0v f osc3 resistor for oscillation = 100k ? 5.04 5.993 7.04 khz ? kf1 rt0, rt0-1, rt1 = 1khz 8.006 8.210 8.416 ? ? kf2 rt0, rt0-1, rt1 = 10khz 0.99 1 1.01 ? ? rs to rt oscillation frequency ratio *1 vdd = 3.0v kf3 rt0, rt0-1, rt1 = 100khz 0.100 0.108 0.115 ? ? *1: kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. f oscx (rt0 ? cs0 oscillation) f oscx (rt0-1 ? cs0 oscillation) f oscx (rt1 ? cs1 oscillation) kfx = f oscx (rs0 ? cs0 oscillation) , f oscx (rs0 ? cs0 oscillation) , f oscx (rs1 ? cs1 oscillation) (x = 1, 2, 3) note: - please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistor s and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on the wires may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. - when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have vss(gnd) trace next to the signal. - please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. v dd av dd v ref v ddl v ddx c l1 c l0 c x v ss av ss c v rt0, rt0-1, rt1: 1k ? /10k ? /100k ? rs0, rs1: 10k ? cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm frequency measurement (f oscx ) input pins vih vil *1: input logic circuit to determine the specified measuring conditions. (*1) cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 rt1 in0 cvr0 cvr1
fedl610421-01 lapis semiconductor ML610421/ml610422 33/36 electrical characteristics of successive approximation type a/d converter (v dd = 1.8 to 3.6v, av dd = 2.2 to 3.6v, v ss = av ss = 0v, ta = ? 20 to +70 ? c, ta = ? 40 to +85 ? c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit resolution n ?? ?? ?? 12 bit 2.7v ? v ref ? 3.6v ? 4 ?? +4 integral non-linearity error idl 2.2v ? v ref ? 2.7v ? 6 ?? +6 2.7v ? v ref ? 3.6v ? 3 ?? +3 differential non-linearity error dnl 2.2v ? v ref ? 2.7v ? 5 ?? +5 zero-scale error v off ?? ? 6 ?? +6 full-scale error fse ?? ? 6 ?? +6 lsb reference voltage v ref ?? 2.2 ?? av dd v sack = 0 (hsclk = 375khz to 625khz) ?? 25 ?? conversion time t conv sack = 1 (hsclk = 1.5mhz to 4.2mhz) ?? 112 ?? ? /ch ? : period of high-speed clock (hsclk) a v dd av dd v ref v ddl v ddx v ss av ss analog input 1 ? f ?? ri ? 5k ? 0.1 ? f 0.1 ? f ain0, ain1 10 ? f 0.1 ? f + 1 ? f reference voltage
fedl610421-01 lapis semiconductor ML610421/ml610422 34/36 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedl610421-01 lapis semiconductor ML610421/ml610422 35/36 revision history page document no. date previous edition current edition description fedl610421-01 apr. 12, 2011 ? ? formally edition 1
fedl610421-01 lapis semiconductor ML610421/ml610422 36/36 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such in formation, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be us ed with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the pr oducts safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

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